1. Technical Field
Various example embodiments may generally relate to a unit delay circuit and digitally controlled delay line including the unit delay circuit where a glitch is not generated when a delay code changes.
2. Related Art
A conventional digitally controlled delay line delays an input signal by a delay amount corresponding to a delay code and outputs the delayed input signal.
The delay code can be changed and input with different values over time.
A glitch can be generated in the output signal of the digitally controlled delay line when the delay code is variably input.
When the input signal is delayed and output, a glitch may have occurred if the number of edges of the input signal and the output signal are different.
If a glitch occurred, a malfunction may be caused in a circuit using the output signal of the delay line.
For example, in a system that operates synchronously with a clock signal, if the number of edges between the input and output clock signals are different, a malfunction may occur in which states vary differently from the design.
Accordingly, there is a demand for a digitally controlled delay line in which a glitch is not generated in an output signal when a delay code is changed.